From 8be7a2fd46155d29f7202c4a7b85b078f8cf96c1 Mon Sep 17 00:00:00 2001 From: Keir Fraser Date: Tue, 6 May 2008 10:25:34 +0100 Subject: [PATCH] x86, Intel: Make only EST feature visible to dom0 to enable Cx-state logic. There should be no need to make MWAIT visible. Signed-off-by: Keir Fraser --- xen/arch/x86/traps.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index ebdf25db4f..54776ccc8c 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -713,8 +713,7 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs) __clear_bit(X86_FEATURE_PBE, &d); __clear_bit(X86_FEATURE_DTES64 % 32, &c); - if ( !IS_PRIV(current->domain) ) - __clear_bit(X86_FEATURE_MWAIT % 32, &c); + __clear_bit(X86_FEATURE_MWAIT % 32, &c); __clear_bit(X86_FEATURE_DSCPL % 32, &c); __clear_bit(X86_FEATURE_VMXE % 32, &c); __clear_bit(X86_FEATURE_SMXE % 32, &c); @@ -2148,9 +2147,8 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) case MSR_IA32_MISC_ENABLE: if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) ) goto fail; - regs->eax &= ~MSR_IA32_MISC_ENABLE_PERF_AVAIL; - if ( !IS_PRIV(current->domain) ) - regs->eax &= ~MSR_IA32_MISC_ENABLE_MONITOR_ENABLE; + regs->eax &= ~(MSR_IA32_MISC_ENABLE_PERF_AVAIL | + MSR_IA32_MISC_ENABLE_MONITOR_ENABLE); regs->eax |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | MSR_IA32_MISC_ENABLE_XTPR_DISABLE; -- 2.30.2